1. Field of the Invention
The invention disclosed herein relates generally to the circuit design and configuration of power MOSFET based devices. More particularly, this invention relates to a novel and improved circuit configuration designs and manufacturing methods for providing current limited bi-lateral MOSFET switches.
2. Description of the Prior Art
Conventional technologies and circuit designs for current limited bilateral switch implemented with FET based transistors are still limited by a technical difficulty that the switching resistance is high and cannot be conveniently implemented in device where higher power efficiency is required. As will be further discussed below specifically, combinations of circuits employed to enable bilateral switch and also limiting the current often inadvertently increase the switching resistance. The increase in switch resistance inevitably leads to the undesirable effects of power wastes, loss of efficiency and heat generations. The technical difficulty thus limits the application of the FET-based bilateral switches to many applications while there are increasing demands to provide effective and conveniently integration FET based power devices and power switches.
A bilateral power switch implemented with common source P-FET transistors Q1 and Q2 is shown in FIGS. 1A and 1B. The power switch is applied for transferring power from a power source to a load connected between a ground voltage and Vout with current Iload flowing through the load. The transistor Q1 is a PMOS based switch that switches off the current flow between the terminals of Vin and Vout in an off state. The second PMOS transistor Q2 connected in parallel to the transistor Q1 between the input and output voltages serve a function to prevent a current to pass from the Vout terminal to the Vin terminal during an off state as that shown in FIG. 1B. Effectively, in an off state the two back-to-back body-to-drain diodes ensure the current cannot flow in either direction. For the purpose to ensure the bilateral OFF operations as described above, the gate voltage applied to the gate terminals of Q1 and Q2 are selected as a higher voltage between the Vin and Vout.
FIGS. 2A and 2B show an alternate bilateral switch implemented with NMOS transistors. In order to ensure the NMOS transistors have enough gate overdrive (Vgs−Vth), a charge pump is necessary to lift the gate voltage to twice that of Vin, or Vgs=Vin. A 2× charge pump is usually sufficient. However, depending on the FET, 3× or even 4× Vin may be necessary at times to provide sufficient gate overdrive.
As shown in FIGS. 1A, 1B and 2A and 2B, the two MOSFET transistors as implemented in the bilateral power switches can be connected in either a common drain or common source configuration. The same blocking effect is achieved in an OFF state in either of bilateral switches as shown. Although such bilateral switches have a reduced power carrying capability due to a Rdson that is twice that of the switches implemented with a single FET transistor, the bilateral stand-off capability makes it an acceptable trade-off.
In addition to the requirement to totally switch off the reverse current, there is also a need to limit the current passing through the load. A current limiting switch that is implemented with a P-channel power MOSFET Q1 is shown in FIG. 3A. When the load starts to draw excessive current, the current limiting switch stabilizes the load current to a pre-set value irrespective of the load resistance and holds the current at that preset value indefinitely, or until other protection circuitry, such as a thermal shutdown, is activated. The primary control circuitry consists of a sense resistor, Rs, and an amplifier, A1. When the load current is low and voltage drop across the sense resistor is lower than Vlim, the output voltage (Vdrv) of A1 is driven to ground rail and the Q1 switch is fully turned on. When Vs is increased to Vlim, the amplifier A1 drives the gate of Q1, or Vdrv, higher which results in reduced gate drive to Q1 and forcing the device into saturation region of operation. Continued pulling down action by the load will eventually drive Vout to near ground but the load current will stay at the value set by Vlim/Rs. Once the load is removed, Vs reduces to zero and A1 will return the gate of Q1 to ground and back to fully ON state.
FIG. 3B shows an alternate current limiting switch implemented with an N-channel Power transistor. Since the required charge pump for the NMOS gate drive often has high output impedance, when integrated into an IC, it is usually not possible to power the amplifier A1 directly from the charge pump. A method frequently used is to reduce the charge pump output (Vdrv) by pulling down the output with an Ipd driver shown in FIG. 3B, otherwise, the current regulation function is carried out exactly the same as that performed by the PMOS switch as that shown and described in FIG. 3A.
Conventional bilateral current limited switches are configured by a combination of the bilateral switches as that shown in FIGS. 1A, 1B, 2A and 2B with the current limiting sensing resistor implemented in the current limited switch shown in FIGS. 3A and 3B. FIG. 4A shows such a current limited bilateral PMOS power switch and FIG. 4B shows a similar switch configured based on an NMOS power transistor. The operations of the bilateral switch and the current limiting function performed by these bilateral current limited switches shown in FIGS. 4A and 4B are self-evident from the above descriptions.
Even though the bilateral current limited switches as shown in FIGS. 4A and 4B are functional to totally switch off the current during an off state and is able to limit a load current to a preset value. However, such switches present a severe technical difficulty due to a high switch resistance when a switch is configured with such combination of circuits. Specifically, the switch resistance is now increased to a value 2×Rdson+Rs. For high power applications, such bilateral switches often present high power consumption and low operational efficiency and would not be acceptable.
Therefore, a need still exists in the art to provide an improved device configuration and manufacturing methods to provide FET based bilateral current limited switches with reduced switch resistance such that the above-discussed technical difficulties can be resolved.